Integrated circuits (IC) provide the pathways for signal transport in an electrical device. An IC in a device is composed of a number of active transistors contained in a silicon base layer of a semiconductor substrate. To increase the capacity of an IC, large numbers of interconnections with metal “wires” are made between one active transistor in the silicon base of the substrate and another active transistor in the silicon base of the substrate. The interconnections, collectively known as the metal interconnection of a circuit, are made through holes, vias or trenches that are cut into a substrate. The particular point of the metal interconnection which actually makes contact with the silicon base is known as the contact. The remainder of the hole, via or trench is filled with a conductive material, termed a contact plug. As transistor densities continue to increase, forming higher level integrated circuits, the diameter of the contact plug must decrease to allow for the increased number of interconnections, multilevel metallization structures and higher aspect ratio vias.
Aluminum has been the accepted standard for contacts and interconnections in integrated circuits. However, problems with its electromigration and its high electrical resistivity require new materials for newer structures with submicron dimensions. Copper holds promise as the interconnect material for the next generation of integrated circuits in ultra large scale integration (ULSI) circuitry, yet its formation of copper silicide (Cu—Si) compounds at low temperatures and its electromigration through a silicon oxide (SiO2) are disadvantages to its use.
As the shift from aluminum to copper as an interconnect element of choice occurs, new materials are required to serve as a barrier, preventing copper diffusion into the underlying dielectric layers of the substrate. New materials are also required to serve as a liner, adhering subsequently deposited copper to the substrate. The liner must also provide a low electrical resistance interface between copper and the barrier material. Barrier layers that were previously used with aluminum, such as titanium (Ti) and titanium nitride (TiN) barrier layers deposited either by physical vapor deposition (PVD) methods such as sputtering and/or chemical vapor deposition (CVD), are ineffective as barriers to copper. In addition, Ti reacts with copper to form copper titanium compounds at the relatively low temperatures used with PVD and/or CVD.
Sputtered tantalum (Ta) and reactive sputtered tantalum nitride (TaN) have been demonstrated to be good diffusion barriers between copper and a silicon substrate due to their high conductivity, high thermal stability and resistance to diffusion of foreign atoms. However, the deposited Ta and/or TaN film has inherently poor step coverage due to its shadowing effects. Thus the sputtering process is limited to relatively large feature sizes (>0.3 μm) and small aspect ratio contact vias. CVD offers the inherent advantage over PVD of better conformality, even in small structures (<0.2 μm) with high aspect ratios. However, CVD of Ta and TaN with metal-organic sources such as tertbutylimidotris (diethylamido)tantalum TBTDET, pentakis (dimethylamino) tantalum (PDMAT) and pentakis (diethylamnio) tantalum (PDEAT) yields mixed results. Additional problems with Ta and TaN are that all resulting films have relatively high concentrations of oxygen and carbon impurities and require the use of a carrier gas.
The need to use a carrier gas presents the disadvantage that the concentration of the precursor gas in the carrier is not precisely known. As a result, accurate metering of a mixture of a carrier gas and a precursor gas to the CVD reaction chamber does not insure accurate metering of the precursor gas alone to the reactor. This can cause the reactants in the CVD chamber to be either too rich or too lean. The use of a carrier gas also presents the disadvantage that particulates are frequently picked up by the flowing carrier gas and delivered as contaminants to the CVD reaction chamber. Particulates on the surface of a semiconductor wafer during processing can result in the production of defective semiconductor devices.
Thus, a process to deposit TaN at the relatively low temperatures used in PECVD (<500° C.) would provide an advantage in the formation of copper barriers in the next generation of IC. Ideally, the deposited film will have a high step coverage (the ratio of the coating thickness at the bottom of a feature to the thickness on the sides of a feature or on the top surface of the substrate or wafer adjacent the feature), good diffusion barrier properties, minimal impurities, low resistivity, good conformality (even coverage of complex topography of high aspect ratio features) and ideally the process will have a high deposition rate.